1. Field of the Invention
The present invention relates generally to clock signals in a digital system. Still more particularly, the present invention relates to the reduction of skew between output clock signals from a clock buffer. Still more particularly, the invention relates to buffer-to-buffer skew reduction by coupling together the output clock signals from a clock buffer.
2. Background of the Invention
The timing of a microprocessor-based circuit is controlled by one or more clock signals. As shown in FIG. 1, a clock signal includes periodic transitions between high (logic "1") and low (logic "0") logic levels at a rate typically described in terms of frequency. Frequency commonly is measured by the number of high/low transitions or cycles that occur each second. Thus, a frequency of 1 Hertz (1 Hz) refers to one high/low cycle occurring each second. Early personal computers operated using clock signals with a frequency of approximately 5 megahertz (MHz) indicating that the clock signal had 5,000,000 cycles each second. Current implementations of personal computers include numerous clock sources with frequencies ranging from 1-200 MHz.
The clock signal in a computer system is used to synchronize bus cycles in the system. Thus, all digital components in the computer system initiate data operations based upon the clock signal. More specifically, circuit components that use a clock signal change the state of their output signals in conjunction with the rising and/or falling edge of the clock signal. For example, in FIG. 1, rising edge 17 or falling edge 18 might be used to control the state of a given circuit component.
Clock signals usually are generated by clock circuits which include multiple clock signal sources (i.e., output buffers for providing a clock signal). Like most digital circuitry, clock circuits typically are fabricated on a printed circuit board. Microprocessor-based circuits are often complex and include numerous electrical components, many of which are driven by a clock signal. Most, if not all, microprocessor-based circuits include multiple clock signals, typically one clock signal source for each destination point requiring a clock signal. The use of multiple clock signals is necessary for numerous reasons such as providing sufficient drive current for all loads requiring a clock signal and improving clock signal quality.
Referring now to FIG. 2, a typical clock circuit 10 includes an oscillator circuit 12 coupled to a clock buffer 14. The oscillator circuit 12 generates a periodic signal at a predetermined frequency. The clock buffer 14 receives the periodic signals from oscillator circuit 12 and generates n output clock signals, labeled in FIG. 2 as clock0, clock1, clock2, through clockn. The output clock signals are produced by output buffers (not shown) in clock buffer 14. The n clock signals couple to multiple destination points D.sub.1, D.sub.2, D.sub.3, through D.sub.n through output series termination resistors R.sub.0. The clock signals then are used to drive circuit components located at various sites across the circuit board in accordance with known techniques.
Although occurring extremely rapidly, electrical signals require a finite amount of time to travel from one point to another on a circuit board. The longer the distance through which a signal must travel, the more time it takes for that signal to propagate the required distance. Conductive copper pathways, commonly called traces, are etched in the circuit board to provide conductive paths for signals to travel from one component to another. The length of the traces between output resistors R.sub.0 and the various destination points D.sub.0, D.sub.1, D.sub.2, D.sub.n are labeled as L.sub.0, L.sub.1, L.sub.2, L.sub.n in FIG. 2. For example, L.sub.0 refers to the distance between resistor R.sub.0 and destination point D.sub.0. As illustrated in FIG. 2, L.sub.n represents a longer distance than L.sub.0. Thus, the time it takes for signal clockn to propagate through trace length L.sub.n to destination point D.sub.n is greater than for clock0 to propagate through trace distance L.sub.0. Thus, if the four clock signals clock0, clock1, clock2, clockn are in phase (i.e., their rising and falling edges occur simultaneously)at resistor R.sub.0, the rising and falling edges of the clock signals at the destination points will be out of phase. Specifically, the clock signal that propagates through the shortest trace length will have a rising and falling edge that occurs before the associated rising and falling edges of the other clock signals. Moreover, if all of the trace lengths are of different lengths, then all of the clock signals will have rising or falling edges that are out of phase at the respective destination points D.sub.0, D.sub.1, D.sub.2, D.sub.n. This phase difference typically is referred to as skew. FIG. 3 illustrates the effects of skewing in the prior art circuit of FIG. 2. Approximately two cycles of clock signals clock0-clockn are shown in which the rising edges 17a, 17b, 17c, 17d are not in phase. Because of the skew between clock signals, the circuit components in a computer, such as address and data latches and state machine flip flops, will change state at different times potentially impairing the performance of the computer system.
The skew between clock signals is further exacerbated by the clock buffer. Typical clock buffers do not produce identical clock signals; that is, the rising and falling edges of the output clock signals do not all occur simultaneously. The maximum skew between the clock signals shown in FIG. 3 is time interval S occurring between the rising edge 17a of clock0 and the rising edge 17d of clockn. Clock buffer manufacturers usually specify a time value for the maximum amount of skew the part may produce. The maximum skew value usually is referred to as buffer-to-buffer skew, referring to the output buffers that drive a clock signal on each of the output terminals of the clock buffer. The maximum buffer-to-buffer skew, for example, for the CGS2535 clock buffer manufactured by National Semiconductor is 250 picoseconds (ps). In computer systems in which speed is of paramount concern, a 250 ps buffer-to-buffer skew represents a significant amount of skewing and may impair the performance of the computer. Thus, reducing or eliminating buffer-to-buffer skew would be beneficial.
At least two attempts have been made to correct or reduce skew in a clock distribution system. In one technique, a prototype circuit board is constructed and the amount of inter-clock signal skew is measured at the destination points. Then the layout of the traces on the printed circuit board is modified to add additional trace length to the faster clock signal traces so that all of the clock signals are substantially in phase at the destination points. This technique thus compensates for skew at the destination points, but does not reduce buffer-to-buffer skew at the clock buffer (i.e., buffer-to-buffer skew is still present at the outputs of the clock buffer). Further, this process is time consuming and expensive, in that the fabrication and testing of a prototype board is required with the subsequent modifications to add precise lengths of additional trace to compensate for the clock signal skew.
A second attempt at overcoming the skew problem is exemplified in FIG. 4. As shown in FIG. 4, 16 output clock signals (i.e., n=16) are shown for clock buffer 14. In this approach, which currently is used in the Compaq Proliant 5000 computer, a trace 50 electrically couples together all of the output terminals of clock buffer 14 in an attempt to produce a single clock signal on trace 50. This single clock signal then is provided to various destination points via output resistors R.sub.0. Although this approach may reduce buffer-to-buffer skew somewhat, a substantial amount of skew remains that cannot be reduced further by trace 50. The substantial amount of skew still present in the clock signals results from differences in the trace lengths between the various clock buffer output terminals and the termination resistors R.sub.0.
A large portion of the total amount of skewing between clock signals is caused by the clock buffer. Thus, it would be advantageous to reduce, and preferably eliminate, buffer-to-buffer skewing associated with clock buffers. As a direct consequence, computers, and other digital systems, with multiple clock signals could operate faster and more robustly. Despite the advantages such a system would provide, there currently is no system which substantially eliminates the problem with buffer-to-buffer skewing in clock circuits.